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tps54560 www.ti.com slvsbn0 ? march 2013 4.5 v to 60 v input, 5 a, step down dc-dc converter with eco-mode ? check for samples: tps54560 1 features 2 ? high efficiency at light loads with pulse ? 8-pin hsoic with powerpad ? package skipping eco-mode ? ? ? 40 c to 150 c t j operating range ? 92-m high-side mosfet ? supported by webench ? software tool ? 146 a operating quiescent current and 2 a shutdown current applications ? 100 khz to 2.5 mhz fixed switching frequency ? industrial automation and motor control ? synchronizes to external clock ? vehicle accessories: gps, entertainment ? low dropout at light loads with integrated ? usb dedicated charging ports and battery boot recharge fet chargers ? adjustable uvlo voltage and hysteresis ? 12 v, 24 v and 48 v industrial, automotive and communications power systems ? 0.8 v 1% internal voltage reference description the tps54560 is a 60 v, 5 a, step down regulator with an integrated high side mosfet. the device survives load dump pulses up to 65v per iso 7637. current mode control provides simple external compensation and flexible component selection. a low ripple pulse skip mode reduces the no load supply current to 146 a. shutdown supply current is reduced to 2 a when the enable pin is pulled low. undervoltage lockout is internally set at 4.3 v but can be increased using the enable pin. the output voltage start up ramp is internally controlled to provide a controlled start up and eliminate overshoot. a wide switching frequency range allows either efficiency or external component size to be optimized. output current is limited cycle-by-cycle. frequency foldback and thermal shutdown protects internal and external components during an overload condition. the tps54560 is available in an 8-pin thermally enhanced hsoic powerpad ? package. simplified schematic efficiency vs load current 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 eco-mode, powerpad, webench are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. sw vin gnd boot fb comp tps54560 en rt/clk v in v out 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 efficiency (%) i o - output current (a) c024 v out = 12 v, f sw = 800khz, v out = 5 v and 3.3 v, f sw = 400 khz 12 v to 5 v 12 v to 3.3 v 36 v to 12 v
tps54560 slvsbn0 ? march 2013 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. table 1. ordering information (1) t j package part number (2) ? 40 c to 150 c 8 pin hsoic TPS54560DDA (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) the dda package is also available in tape and reel packaging. add an r suffix to the device type (TPS54560DDAr). device information pin configuration hsoic package (top view) pin functions pin i/o description name no. a bootstrap capacitor is required between boot and sw. if the voltage on this capacitor is below the boot 1 o minimum required to operate the high side mosfet, the output is switched off until the capacitor is refreshed. vin 2 i input supply voltage with 4.5 v to 60 v operating range. enable pin, with internal pull-up current source. pull below 1.2 v to disable. float to enable. adjust the input en 3 i undervoltage lockout with two resistors. see the enable and adjusting undervoltage lockout section. resistor timing and external clock. an internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. if the pin is pulled above the pll upper threshold, rt/clk 4 i a mode change occurs and the pin becomes a synchronization input. the internal amplifier is disabled and the pin is a high impedance clock input to the internal pll. if clocking edges stop, the internal amplifier is re- enabled and the operating mode returns to resistor frequency programming. fb 5 i inverting input of the transconductance (gm) error amplifier. error amplifier output and input to the output switch current (pwm) comparator. connect frequency comp 6 o compensation components to this pin. gnd 7 ? ground sw 8 i the source of the internal high-side power mosfet and switching node of the converter. thermal pad 9 ? gnd pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. 2 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 gnd 7 comp 6 fb 5 sw 8 23 4 1 vin en rt/clk boot thermal pad 9
tps54560 www.ti.com slvsbn0 ? march 2013 functional block diagram copyright ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: tps54560 error amplifier boot charge boot uvlo uvlo current sense oscillator with pll frequency foldback logic slope compensation pwm comparator minimum clamp pulse skip maximum clamp voltage reference reference dac for soft - start fb comp rt/ clk sw boot vin gnd thermal shutdown en enable comparator shutdown logic shutdown enable threshold 6 8/8/ 2012 a 0192789 logic shutdown powerpad shutdown ov
tps54560 slvsbn0 ? march 2013 www.ti.com absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) value unit min max vin ? 0.3 65 en ? 0.3 8.4 boot 73 input voltage v fb ? 0.3 3 comp ? 0.3 3 rt/clk ? 0.3 3.6 boot-sw 8 output voltage sw ? 0.6 65 v sw, 10-ns transient ? 2 65 electrostatic discharge (hbm) qss 009-105 (jesd22-a114a) 2 kv electrostatic discharge (cdm) qss 009-147 (jesd22-c101b.01) 500 v operating junction temperature ? 40 to 150 c storage temperature ? 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. thermal information tps54560 thermal metric (1) (2) units dda (8 pins) ja junction-to-ambient thermal resistance (standard board) 42.0 jt junction-to-top characterization parameter 5.9 jb junction-to-board characterization parameter 23.4 c/w jctop junction-to-case(top) thermal resistance 45.8 jcbot junction-to-case(bottom) thermal resistance 3.6 jb junction-to-board thermal resistance 23.4 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) power rating at a specific ambient temperature ta should be determined with a junction temperature of 150 c. this is the point where distortion starts to substantially increase. see power dissipation estimate in application section of this data sheet for more information. 4 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560
tps54560 www.ti.com slvsbn0 ? march 2013 electrical characteristics t j = ? 40 c to 150 c, vin = 4.5 to 60v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin pin) operating input voltage 4.5 60 v internal undervoltage lockout threshold rising 4.1 4.3 4.48 v internal undervoltage lockout threshold 325 mv hysteresis shutdown supply current en = 0 v, 25 c, 4.5 v vin 60 v 2.25 4.5 a operating: nonswitching supply current fb = 0.83 v, t a = 25 c 146 175 enable and uvlo (en pin) enable threshold voltage no voltage hysteresis, rising and falling 1.1 1.2 1.3 v enable threshold +50 mv ? 4.6 input current a enable threshold ? 50 mv ? 0.58 ? 1.2 -1.8 hysteresis current ? 2.2 ? 3.4 -4.5 a enable to comp active v in = 12 v, t a = 25 c 540 s internal soft-start time soft-start time f sw = 500 khz, 10% to 90% 2.1 ms soft-start time f sw = 2.5 mhz, 10% to 90% 0.42 ms voltage reference voltage reference 0.792 0.8 0.808 v high-side mosfet on-resistance vin = 12 v, boot-sw = 6 v 92 190 m error amplifier input current 50 na error amplifier transconductance (g m ) ? 2 a < i comp < 2 a, v comp = 1 v 350 mhos error amplifier transconductance (g m ) during ? 2 a < i comp < 2 a, v comp = 1 v, v fb = 0.4 v 77 mhos soft-start error amplifier dc gain v fb = 0.8 v 10,000 v/v min unity gain bandwidth 2500 khz error amplifier source/sink v (comp) = 1 v, 100 mv overdrive 30 a comp to sw current transconductance 17 a/v current limit all vin and temperatures, open loop (1) 6.3 7.5 8.8 current limit threshold all temperatures, vin = 12 v, open loop (1) 6.3 7.5 8.3 a vin = 12 v, t a = 25 c, open loop (1) 7.1 7.5 7.9 current limit threshold delay 60 ns thermal shutdown thermal shutdown 176 c thermal shutdown hysteresis 12 c timing resistor and external clock (rt/clk pin) switching frequency range using rt mode 100 2500 khz f sw switching frequency r t = 200 k 450 500 550 khz switching frequency range using clk mode 160 2300 khz minimum clk input pulse width 15 ns rt/clk high threshold 1.55 1.7 v rt/clk low threshold 0.5 1.2 v rt/clk falling edge to sw rising edge measured at 500 khz with rt resistor in series 55 ns delay pll lock in time measured at 500 khz 78 s (1) open loop current limit measured directly at the sw pin and is independent of the inductor value and slope compensation. copyright ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: tps54560
tps54560 slvsbn0 ? march 2013 www.ti.com typical characteristics on resistance vs junction temperature voltage reference vs junction temperature figure 1. figure 2. switch current limit vs junction temperature switch current limit vs input voltage figure 3. figure 4. switching frequency vs rt/clk resistance switching frequency vs junction temperature high frequency range figure 5. figure 6. 6 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 0 0.05 0.1 0.15 0.2 0.25 50 25 0 25 50 75 100 125 150 r dson - on-state resistance ( ) t j - junction temperature ( ? c) boot-sw = 3 v boot-sw = 6 v c025 0.784 0.789 0.794 0.799 0.804 0.809 0.814 50 25 0 25 50 75 100 125 150 v fb - voltage referance ( v) t j - junction temperature ( ? c) series1 c026 v in = 12 v 450 460 470 480 490 500 510 520 530 540 550 50 25 0 25 50 75 100 125 150 f s - switching frequency (khz) t j - junction temperature ( ? c) series1 c029 r t = 200 k , v in = 12 v 100 150 200 250 300 350 400 450 500 200 300 400 500 600 700 800 900 1000 f sw - switching frequency (khz) rt/clk - resistance (k ) c030 f sw (khz) = 92417 x r t (k ) 0.991 r t (k ) = 101756 x f sw (khz) 1.008 6 6.5 7 7.5 8 8.5 9 50 25 0 25 50 75 100 125 150 high side switch current (a) t j - junction temperature ( ? c) series2 c027 v in = 12 v 6 6.5 7 7.5 8 8.5 9 0 10 20 30 40 50 60 high side switch current (a) v i - input voltage (v) series1 series2 series4 c028 40 ? c 25 ? c 150 ? c
tps54560 www.ti.com slvsbn0 ? march 2013 typical characteristics (continued) switching frequency vs rt/clk resistance low frequency range ea transconductance vs junction temperature figure 7. figure 8. ea transconductance during soft-start vs junction temperature en pin voltage vs junction temperature figure 9. figure 10. en pin current vs junction temperature en pin current vs junction temperature figure 11. figure 12. copyright ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: tps54560 5.5 5.3 5.1 4.9 4.7 4.5 4.3 4.1 3.9 3.7 3.5 50 25 0 25 50 75 100 125 150 i en (ua) t j - junction temperature ( ? c) c035 v in = 12 v, i en = threshold + 50 mv 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 50 25 0 25 50 75 100 125 150 i en (a) t j - junction temperature ( ? c) series2 c036 v in = 12v, i en = threshold 50 mv 20 30 40 50 60 70 80 90 100 110 120 50 25 0 25 50 75 100 125 150 gm (a/v) t j - junction temperature ( ? c) series2 c033 v in = 12 v 1.15 1.16 1.17 1.18 1.19 1.2 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.3 50 25 0 25 50 75 100 125 150 en - threshold (v) t j - junction temperature ( ? c) series2 c034 v in = 12 v 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 0 50 100 150 200 f sw - switching frequency (khz) rt/clk - resistance (k ) c031 200 250 300 350 400 450 500 50 25 0 25 50 75 100 125 150 gm (a/v) t j - junction temperature ( ? c) series2 c032 v in = 12 v
tps54560 slvsbn0 ? march 2013 www.ti.com typical characteristics (continued) en pin current hysteresis vs junction temperature switching frequency vs v sense figure 13. figure 14. shutdown supply current vs junction temperature shutdown supply current vs input voltage (v in ) figure 15. figure 16. v in supply current vs junction temperature v in supply current vs input voltage figure 17. figure 18. 8 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 0 0.5 1 1.5 2 2.5 3 0 10 20 30 40 50 60 i vin (a) v in - input voltage (v) series2 c040 t j = 25 ? c 4.5 4.3 4.1 3.9 3.7 3.5 3.3 3.1 2.9 2.7 2.5 50 25 0 25 50 75 100 125 150 i en - hysteresis (a) t j - junction temperature ( ? c) series2 c037 v in = 12 v 0 25 50 75 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 % of nominal switching frequency v sense (v) series2 series4 c038 v sense falling v sense rising 70 90 110 130 150 170 190 210 50 25 0 25 50 75 100 125 150 i vin (a) t j - junction temperature ( ? c) series2 c041 v in = 12 v 70 90 110 130 150 170 190 210 0 10 20 30 40 50 60 i vin (a) v in - input voltage (v) series2 c042 t j = 25 ? c 0 0.5 1 1.5 2 2.5 3 50 25 0 25 50 75 100 125 150 i vin (a) t j - junction temperature ( ? c) series1 c039 v in = 12 v
tps54560 www.ti.com slvsbn0 ? march 2013 typical characteristics (continued) boot-sw uvlo vs junction temperature input voltage uvlo vs junction temperature figure 19. figure 20. soft-start time vs switching frequency 5 v start and stop voltage figure 21. figure 22. copyright ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: tps54560 0 1 2 3 4 5 6 7 8 9 10 100 300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 soft-start time (ms) switching frequency (khz) 12 v, 25 c c045 12 v, 25 ? c 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 5.6 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 v in (v) output current (a) start stop c046 dropout voltage dropout voltage 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 50 25 0 25 50 75 100 125 150 v in (v) t j - junction temperature ( ? c) uvlo start switching uvlo stop switching c044 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 50 25 0 25 50 75 100 125 150 v i - boot-ph (v) t j - junction temperature ( ? c) boot-ph uvlo falling boot-ph uvlo rising c043
tps54560 slvsbn0 ? march 2013 www.ti.com overview the tps54560 is a 60 v, 5 a, step-down (buck) regulator with an integrated high side n-channel mosfet. the device implements constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation. the wide switching frequency range of 100 khz to 2500 khz allows either efficiency or size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground connected to the rt/clk pin. the device has an internal phase-locked loop (pll) connected to the rt/clk pin that will synchronize the power switch turn on to a falling edge of an external clock signal. the tps54560 has a default input start-up voltage of approximately 4.3 v. the en pin can be used to adjust the input voltage undervoltage lockout (uvlo) threshold with two external resistors. an internal pull up current source enables operation when the en pin is floating. the operating current is 146 a under no load condition (not switching). when the device is disabled, the supply current is 2 a. the integrated 92m high side mosfet supports high efficiency power supply designs capable of delivering 5 amperes of continuous current to a load. the gate drive bias voltage for the integrated high side mosfet is supplied by a bootstrap capacitor connected from the boot to sw pins. the tps54560 reduces the external component count by integrating the bootstrap recharge diode. the boot pin capacitor voltage is monitored by a uvlo circuit which turns off the high side mosfet when the boot to sw voltage falls below a preset threshold. an automatic boot capacitor recharge circuit allows the tps54560 to operate at high duty cycles approaching 100%. therefore, the maximum output voltage is near the minimum input supply voltage of the application. the minimum output voltage is the internal 0.8 v feedback reference. output overvoltage transients are minimized by an overvoltage transient protection (ovp) comparator. when the ovp comparator is activated, the high side mosfet is turned off and remains off until the output voltage is less than 106% of the desired output voltage. the tps54560 includes an internal soft-start circuit that slows the output rise time during start-up to reduce in- rush current and output voltage overshoot. output overload conditions reset the soft-start timer. when the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. a frequency foldback circuit reduces the switching frequency during start-up and overcurrent fault conditions to help maintain control of the inductor current. detailed description fixed frequency pwm control the tps54560 uses fixed frequency, peak current mode control with adjustable switching frequency. the output voltage is compared through external resistors connected to the fb pin to an internal voltage reference by an error amplifier. an internal oscillator initiates the turn on of the high side power switch. the error amplifier output at the comp pin controls the high side power switch current. when the high side mosfet switch current reaches the threshold level set by the comp voltage, the power switch is turned off. the comp pin voltage will increase and decrease as the output current increases and decreases. the device implements current limiting by clamping the comp pin voltage to a maximum level. the pulse skipping eco-mode is implemented with a minimum voltage clamp on the comp pin. slope compensation output current the tps54560 adds a compensating ramp to the mosfet switch current sense signal. this slope compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. the peak current limit of the high side switch is not affected by the slope compensation and remains constant over the full duty cycle range. pulse skip eco-mode the tps54560 operates in a pulse skipping eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters eco-mode. the pulse skipping current threshold is the peak switch current level corresponding to a nominal comp voltage of 600 mv. 10 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560
tps54560 www.ti.com slvsbn0 ? march 2013 detailed description (continued) when in eco-mode, the comp pin voltage is clamped at 600 mv and the high side mosfet is inhibited. since the device is not switching, the output voltage begins to decay. the voltage control loop responds to the falling output voltage by increasing the comp pin voltage. the high side mosfet is enabled and switching resumes when the error amplifier lifts comp above the pulse skipping threshold. the output voltage recovers to the regulated value, and comp eventually falls below the eco-mode pulse skipping threshold at which time the device again enters eco-mode. the internal pll remains operational when in eco-mode. when operating at light load currents in eco-mode, the switching transitions occur synchronously with the external clock signal. during eco-mode operation, the tps54560 senses and controls peak switch current, not the average load current. therefore the load current at which the device enters eco-mode is dependent on the output inductor value. the circuit in figure 35 enters eco-mode at about 25.3 ma output current. as the load current approaches zero, the device enters a pulse skip mode during which it draws only 146 a input quiescent current. low dropout operation and bootstrap voltage (boot) the tps54560 provides an integrated bootstrap voltage regulator. a small capacitor between the boot and sw pins provides the gate drive voltage for the high side mosfet. the boot capacitor is refreshed when the high side mosfet is off and the external low side diode conducts. the recommended value of the boot capacitor is 0.1 f. a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10 v or higher is recommended for stable performance over temperature and voltage. when operating with a low voltage difference from input to output, the high side mosfet of the tps54560 will operate at 100% duty cycle as long as the boot to sw pin voltage is greater than 2.1v. when the voltage from boot to sw drops below 2.1v, the high side mosfet is turned off and an integrated low side mosfet pulls sw low to recharge the boot capacitor. to reduce the losses of the small low side mosfet at high output voltages, it is disabled at 24 v output and re-enabled when the output reaches 21.5 v. since the gate drive current sourced from the boot capacitor is small, the high side mosfet can remain on for many switching cycles before the mosfet is turned off to refresh the capacitor. thus the effective duty cycle of the switching regulator can be high, approaching 100%. the effective duty cycle of the converter during dropout is mainly influenced by the voltage drops across the power mosfet, the inductor resistance, the low side diode voltage and the printed circuit board resistance. the start and stop voltage for a typical 5 v output application is shown in figure 23 where the vin voltage is plotted versus load current. the start voltage is defined as the input voltage needed to regulate the output within 1% of nominal. the stop voltage is defined as the input voltage at which the output drops by 5% or where switching stops. during high duty cycle (low dropout) conditions, inductor current ripple increases when the boot capacitor is being recharged resulting in an increase in output voltage ripple. increased ripple occurs when the off time required to recharge the boot capacitor is longer than the high side off time associated with cycle by cycle pwm control. at heavy loads, the minimum input voltage must be increased to insure a monotonic startup. the equation below can be used to calculate the minimum input voltage for this condition. vout_max = dmax x (vin_min - iout_max x r ds(on) + vf) - vf + iout_max x rl where: dmax 0.9 ib2sw = 100 a vf = forward drop of the catch diode tsw = 1 / fsw vb2sw = vboot + vf vboot = (1.41 x v in - 0.554 - vf / tsw - 1.847 x 10 3 x ib2sw) / (1.41 + 1 / tsw) r ds(on) = 1 / (-0.3 x vb2sw 2 + 3.577 x vb2sw - 4.246) spacer copyright ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: tps54560
tps54560 slvsbn0 ? march 2013 www.ti.com detailed description (continued) figure 23. 5v start/stop voltage error amplifier the tps54560 voltage regulation loop is controlled by a transconductance error amplifier. the error amplifier compares the fb pin voltage to the lower of the internal soft-start voltage or the internal 0.8 v voltage reference. the transconductance (gm) of the error amplifier is 350 a/v during normal operation. during soft-start operation, the transconductance is reduced to 78 a/v and the error amplifier is referenced to the internal soft- start voltage. the frequency compensation components (capacitor, series resistor and capacitor) are connected between the error amplifier output comp pin and gnd pin. adjusting the output voltage the internal voltage reference produces a precise 0.8 v 1% voltage reference over the operating temperature and voltage range by scaling the output of a bandgap reference circuit. the output voltage is set by a resistor divider from the output node to the fb pin. it is recommended to use 1% tolerance or better divider resistors. select the low side resistor r ls for the desired divider current and use equation 1 to calculate r hs . to improve efficiency at light loads consider using larger value resistors. however, if the values are too high, the regulator will be more susceptible to noise and voltage errors from the fb input current may become noticeable. (1) enable and adjusting undervoltage lockout the tps54560 is enabled when the vin pin voltage rises above 4.3 v and the en pin voltage exceeds the enable threshold of 1.2 v. the tps54560 is disabled when the vin pin voltage falls below 4 v or when the en pin voltage is below 1.2 v. the en pin has an internal pull-up current source, i1, of 1.2 a that enables operation of the tps54560 when the en pin floats. if an application requires a higher undervoltage lockout (uvlo) threshold, use the circuit shown in figure 24 to adjust the input voltage uvlo with two external resistors. when the en pin voltage exceeds 1.2 v, an additional 3.4 a of hysteresis current, i hys , is sourced out of the en pin. when the en pin is pulled below 1.2 v, the 3.4 a ihys current is removed. this additional current facilitates adjustable input voltage uvlo hysteresis. use equation 2 to calculate r uvlo1 for the desired uvlo hysteresis voltage. use equation 3 to calculate r uvlo2 for the desired vin start voltage. in applications designed to start at relatively low input voltages (that is, from 4.5 v to 9 v) and withstand high input voltages (that is, from 40 v to 60 v), the en pin may experience a voltage greater than the absolute maximum voltage of 8.4 v during the high input voltage condition. to avoid exceeding this voltage when using the en resistors, the en pin is clamped internally with a 5.8 v zener diode that will sink up to 150 a. 12 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 hs ls vout 0.8v r = r 0.8 v - ? ? ? ? 4.7 0 0.1 0.15 0.35 0.5 load current - a v - input voltage - v i start stop 4.8 4.9 5 5.1 5.34.6 5.4 5.5 5.65.2 0.05 0.25 0.2 0.3 0.4 0.45 dropout voltage dropout voltage
tps54560 www.ti.com slvsbn0 ? march 2013 detailed description (continued) figure 24. adjustable undervoltage lockout figure 25. (uvlo) (2) (3) internal soft-start the tps54560 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value in 1024 switching cycles. the internal soft-start time (10% to 90%) is calculated using equation 4 (4) if the en pin is pulled below the stop threshold of 1.2 v, switching stops and the internal soft-start resets. the soft-start also resets in thermal shutdown. constant switching frequency and timing resistor (rt/clk) pin) the switching frequency of the tps54560 is adjustable over a wide range from 100 khz to 2500 khz by placing a resistor between the rt/clk pin and gnd pin. the rt/clk pin voltage is typically 0.5 v and must have a resistor to ground to set the switching frequency. to determine the timing resistance for a given switching frequency, use equation 5 or equation 6 or the curves in figure 5 and figure 6 . to reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency, maximum input voltage and minimum controllable on time should be considered. the minimum controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high input to output step down ratios. the maximum switching frequency is also limited by the frequency foldback circuit. a more detailed discussion of the maximum switching frequency is provided in the next section. (5) (6) copyright ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: tps54560 f = ss sw 1024 t (ms) (khz) = - + ena uvlo2 start ena 1 uvlo1 v r v v i r - = start stop uvlo1 hys v v r i tps54560 i vin r uvlo1 r uvlo2 en v en ihys 1 vin r uvlo1 r uvlo2 en node 5.8 v 10 k w 1.008 101756 sw (khz) = rt (k ) f w 0.991 92417 rt (k ) = sw (khz) f w
tps54560 slvsbn0 ? march 2013 www.ti.com detailed description (continued) selecting the switching frequency the tps54560 implements peak current mode control in which the comp pin voltage controls the peak current of the high side mosfet. a signal proportional to the high side switch current and the comp pin voltage are compared each cycle. when the peak switch current intersects the comp control voltage, the high side switch is turned off. during overcurrent conditions that pull the output voltage low, the error amplifier increases switch current by driving the comp pin high. the error amplifier output is clamped internally at a level which sets the peak switch current limit. the tps54560 provides an accurate current limit threshold with a typical current limit delay of 60 ns. with smaller inductor values, the delay will result in a higher peak inductor current. the relationship between the inductor value and the peak inductor current is shown in figure 26 . figure 26. current limit delay to protect the converter in overload conditions at higher switching frequencies and input voltages, the tps54560 implements a frequency foldback. the oscillator frequency is divided by 1, 2, 4, and 8 as the fb pin voltage falls from 0.8 v to 0 v. the tps54560 uses a digital frequency foldback to enable synchronization to an external clock during normal start-up and fault conditions. during short-circuit events, the inductor current can exceed the peak current limit because of the high input voltage and the minimum controllable on time. when the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. the frequency foldback effectively increases the off time by increasing the period of the switching cycle providing more time for the inductor current to ramp down. with a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can be controlled by frequency foldback protection. equation 8 calculates the maximum switching frequency at which the inductor current will remain under control when v out is forced to v out(sc) . the selected operating frequency should not exceed the calculated value. equation 7 calculates the maximum switching frequency limitation set by the minimum controllable on time and the input to output step down ratio. setting the switching frequency above this value will cause the regulator to skip switching pulses to achieve the low duty cycle required at maximum input voltage. 14 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 t on t cldelay inductor current (a) clpeak peak inductor current open loop current limit clpeak = v /l x t in cldelay
tps54560 www.ti.com slvsbn0 ? march 2013 detailed description (continued) (7) (8) i o output current i cl current limit rdc inductor resistance v in maximum input voltage v out output voltage v outsc output voltage during short vd diode voltage drop r ds(on) switch on resistance t on controllable on time ? div frequency divide equals (1, 2, 4, or 8) synchronization to rt/clk pin the rt/clk pin can receive a frequency synchronization signal from an external system clock. to implement this synchronization feature connect a square wave to the rt/clk pin through either circuit network shown in figure 27 . the square wave applied to the rt/clk pin must switch lower than 0.5 v and higher than 1.7 v and have a pulsewidth greater than 15 ns. the synchronization frequency range is 160 khz to 2300 khz. the rising edge of the sw will be synchronized to the falling edge of rt/clk pin signal. the external synchronization circuit should be designed such that the default frequency set resistor is connected from the rt/clk pin to ground when the synchronization signal is off. when using a low impedance signal source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor (e.g., 50 ) as shown in figure 27 . the two resistors in series provide the default frequency setting resistance when the signal source is turned off. the sum of the resistance should set the switching frequency close to the external clk frequency. it is recommended to ac couple the synchronization signal through a 10 pf ceramic capacitor to rt/clk pin. the first time the rt/clk is pulled above the pll threshold the tps54560 switches from the rt resistor free- running frequency mode to the pll synchronized mode. the internal 0.5 v voltage source is removed and the rt/clk pin becomes high impedance as the pll starts to lock onto the external signal. the switching frequency can be higher or lower than the frequency set with the rt/clk resistor. the device transitions from the resistor mode to the pll mode and locks onto the external clock frequency within 78 microseconds. during the transition from the pll mode to the resistor programmed mode, the switching frequency will fall to 150 khz and then increase or decrease to the resistor programmed frequency when the 0.5 v bias voltage is reapplied to the rt/clk resistor. the switching frequency is divided by 8, 4, 2, and 1 as the fb pin voltage ramps from 0 to 0.8 volts. the device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up and fault conditions. figure 28 , figure 29 and figure 30 show the device synchronized to an external system clock in continuous conduction mode (ccm), discontinuous conduction (dcm), and pulse skip mode (eco-mode). spacer copyright ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: tps54560 ( ) ( ) f f ? ? + + ? = ? - + ? cl dc d out sc div sw(shift) on in cl d ds on i r v v t v i r v ( ) ( ) o dc out d sw max skip on in o d ds on i r v v 1 t v i r v f ? ? + + ? = ? - + ?
tps54560 slvsbn0 ? march 2013 www.ti.com detailed description (continued) figure 27. synchronizing to a system clock figure 28. plot of synchronizing in ccm figure 29. plot of synchronizing in dcm figure 30. plot of synchronizing in eco-mode 16 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 rt/clk tps54560 clock source pll rt rt/clk tps54560 hi-z clock source pll rt ext il sw ext il sw il ext sw
tps54560 www.ti.com slvsbn0 ? march 2013 detailed description (continued) overvoltage protection the tps54560 incorporates an output overvoltage protection (ovp) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients in designs with low output capacitance. for example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. if the fb pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current limit threshold. when the overload condition is removed, the regulator output rises and the error amplifier output transitions to the normal operating level. in some applications, the power supply output voltage can increase faster than the response of the error amplifier output resulting in an output overshoot. the ovp feature minimizes output overshoot when using a low value output capacitor by comparing the fb pin voltage to the rising ovp threshold which is nominally 109% of the internal voltage reference. if the fb pin voltage is greater than the rising ovp threshold, the high side mosfet is immediately disabled to minimize output overshoot. when the fb voltage drops below the falling ovp threshold which is nominally 106% of the internal voltage reference, the high side mosfet resumes normal operation. thermal shutdown the tps54560 provides an internal thermal shutdown to protect the device when the junction temperature exceeds 176 c. the high side mosfet stops switching when the junction temperature exceeds the thermal trip threshold. once the die temperature falls below 164 c, the device reinitiates the power up sequence controlled by the internal soft-start circuitry. small signal model for loop response figure 31 shows an equivalent model for the tps54560 control loop which can be simulated to check the frequency response and dynamic load response. the error amplifier is a transconductance amplifier with a gm ea of 350 a/v. the error amplifier can be modeled using an ideal voltage controlled current source. the resistor r o and capacitor c o model the open loop gain and frequency response of the amplifier. the 1mv ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. plotting c/a provides the small signal response of the frequency compensation. plotting a/b provides the small signal response of the overall loop. the dynamic loop response can be evaluated by replacing r l with a current source with the appropriate load step amplitude and step rate in a time domain analysis. this equivalent model is only valid for continuous conduction mode (ccm) operation. figure 31. small signal model for loop response copyright ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links: tps54560 fb comp v o r1 r3 c1 c2 r2 co ro gm ea 350 m a/v 0.8 v power stage gm 17 a/v ps sw r esr c out r l b a c
tps54560 slvsbn0 ? march 2013 www.ti.com detailed description (continued) simple small signal model for peak current mode control figure 32 describes a simple small signal model that can be used to design the frequency compensation. the tps54560 power stage can be approximated by a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. the control to output transfer function is shown in equation 9 and consists of a dc gain, one dominant pole, and one esr zero. the quotient of the change in switch current and the change in comp pin voltage (node c in figure 31 ) is the power stage transconductance, gm ps . the gm ps for the tps54560 is 17 a/v. the low-frequency gain of the power stage is the product of the transconductance and the load resistance as shown in equation 10 . as the load current increases and decreases, the low-frequency gain decreases and increases, respectively. this variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see equation 11 ). the combined effect is highlighted by the dashed line in the right half of figure 32 . as the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-db crossover frequency the same with varying load conditions. the type of output capacitor chosen determines whether the esr zero has a profound effect on the frequency compensation design. using high esr aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin is increased by the esr zero of the output capacitor (see equation 12 ). figure 32. simple small signal model and frequency response for peak current mode control 18 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 v o r esr c out r l vc gm ps fp fz adc
tps54560 www.ti.com slvsbn0 ? march 2013 detailed description (continued) (9) (10) (11) (12) small signal model for frequency compensation the tps54560 uses a transconductance amplifier for the error amplifier and supports three of the commonly- used frequency compensation circuits. compensation circuits type 2a, type 2b, and type 1 are shown in figure 33 . type 2 circuits are typically implemented in high bandwidth power-supply designs using low esr output capacitors. the type 1 circuit is used with power-supply designs with high-esr aluminum electrolytic or tantalum capacitors. equation 13 and equation 14 relate the frequency response of the amplifier to the small signal model in figure 33 . the open-loop gain and bandwidth are modeled using the r o and c o shown in figure 33 . see the application section for a design example using a type 2a network with a low esr output capacitor. equation 13 through equation 22 are provided as a reference. an alternative is to use webench software tools to create a design based on the power supply requirements. figure 33. types of frequency compensation copyright ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links: tps54560 vref v o r1 r3 c1 c2 r2 c o r o gm ea comp fb type 2a type 2b type 1 c2 r3 c1 z out esr 1 c r 2 = p f p out l 1 f c r 2 = p ps l adc = gm r z out c p s 1 2 v adc v s 1 2 ? ? + ? p ? = ? ? + ? p ? f f
tps54560 slvsbn0 ? march 2013 www.ti.com detailed description (continued) figure 34. frequency response of the type 2a and type 2b frequency compensation (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) 20 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 1 z1 2 r3 c1 = p 1 p1 2 ro c1 = p ea r2 a1 = gm ro| | r3 r1 + r2 ea r2 a0 = gm ro r1 + r2 f f f z1 p1 p2 s 1 2 ea a0 s s 1 1 2 2 ? ? + ? p ? = ? ? ? ? + + ? ? p p ? ? p ea o gm c = 2 bw (hz) ea aol(v/v) ro = gm a0a1 p1 z1 p2 aol bw p o o 1 p2 = type 1 2 r (c2 + c ) p o o 1 p2 = type 2b 2 r3 | | r c p o o 1 p2 = type 2a 2 r3 | | r (c2 + c )
tps54560 www.ti.com slvsbn0 ? march 2013 application information design guide ? step-by-step design procedure this guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. a few parameters must be known in order to start the design process. these requirements are typically determined at the system level. calculations can be done with the aid of webench or the excel spreadsheet ( slvc452 ) located on the product page. for this example, we will start with the following known parameters: output voltage 5 v transient response 1.25 a to 3.75 a load step v out = 4 % maximum output current 5 a input voltage 12 v nom. 7 v to 60 v output voltage ripple 0.5% of v out start input voltage (rising vin) 6.5 v stop input voltage (falling vin) 5 v selecting the switching frequency the first step is to choose a switching frequency for the regulator. typically, the designer uses the highest switching frequency possible since this produces the smallest solution size. high switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. the switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency foldback protection. equation 7 and equation 8 should be used to calculate the upper limit of the switching frequency for the regulator. choose the lower value result from the two equations. switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit. the typical minimum on time, t onmin , is 135 ns for the tps54560. for this example, the output voltage is 5 v and the maximum input voltage is 60 v, which allows for a maximum switch frequency up to 708 khz to avoid pulse skipping from equation 7 . to ensure overcurrent runaway is not a concern during short circuits use equation 8 to determine the maximum switching frequency for frequency foldback protection. with a maximum input voltage of 60 v, assuming a diode voltage of 0.7 v, inductor resistance of 11 m , switch resistance of 92 m , a current limit value of 6 a and short circuit output voltage of 0.1 v, the maximum switching frequency is 855 khz. for this design, a lower switching frequency of 400 khz is chosen to operate comfortably below the calculated maximums. to determine the timing resistance for a given switching frequency, use equation 5 or the curve in figure 6 . the switching frequency is set by resistor r 3 shown in figure 35 . for 400 khz operation, the closest standard value resistor is 243 k . (23) (24) (25) copyright ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links: tps54560 0.991 92417 rt (k ) = = 244 k 400 (khz) w w sw(shift) 8 6 a x 11 m 0.1 v 0.7 v 855 khz 135 ns 60 v - 6 a x 92 m 0.7 v w + + ? ? = = ? w + ? f sw(max skip) 1 5 a x 11 m 5 v 0.7 v 708 khz 135ns 60 v - 5 a x 92 m 0.7 v w + + ? ? = = ? w + ? f
tps54560 slvsbn0 ? march 2013 www.ti.com figure 35. 5 v output tps54560 design example. output inductor selection (l o ) to calculate the minimum value of the output inductor, use equation 26 . k ind is a ratio that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer, however, the following guidelines may be used. for designs using low esr output capacitors such as ceramics, a value as high as k ind = 0.3 may be desirable. when using higher esr output capacitors, k ind = 0.2 yields better results. since the inductor ripple current is part of the current mode pwm control system, the inductor ripple current should always be greater than 150 ma for stable pwm operation. in a wide input voltage regulator, it is best to choose relatively large inductor ripple current. this provides sufficienct ripple current with the input voltage at the minimum. for this design example, k ind = 0.3 and the inductor value is calculated to be 7.6 h. the nearest standard value is 7.2 h. it is important that the rms current and saturation current ratings of the inductor not be exceeded. the rms and peak inductor current can be found from equation 28 and equation 29 . for this design, the rms inductor current is 5 a and the peak inductor current is 5.8 a. the chosen inductor is a we 7447798720, which has a saturation current rating of 7.9 a and an rms current rating of 6 a. as the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value. the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the tps54560 which is nominally 7.5 a. 22 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 7v to 60v 5v, 5a 1 boot 2 vin 3 en 4 rt/clk 5 fb 6 comp 7 gnd 8 sw 9 pwrpd u1 TPS54560DDA c5 4700pf r4 16.9k c8 47pf c4 0.1uf l1 7.2uh r6 10.2k r5 53.6k r3 243k r1 442k r2 90.9k c1 2.2uf c2 2.2uf d1 b560c c6 47uf c7 47uf c3 2.2uf c10 2.2uf c9 47uf fb vin fb vout
tps54560 www.ti.com slvsbn0 ? march 2013 (26) spacer (27) spacer (28) spacer (29) output capacitor there are three primary considerations for selecting the value of the output capacitor. the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. the output capacitance needs to be selected based on the most stringent of these three criteria. the desired response to a large change in the load current is the first criteria. the output capacitor needs to supply the increased load current until the regulator responds to the load step. the regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. the regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. the output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. equation 30 shows the minimum output capacitance necessary, where i out is the change in output current, ? sw is the regulators switching frequency and v out is the allowable change in the output voltage. for this example, the transient load response is specified as a 4% change in v out for a load step from 1.25 a to 3.75 a. therefore, i out is 3.75 a - 1.25 a = 2.5 a and v out = 0.04 5 = 0.2 v. using these numbers gives a minimum capacitance of 62.5 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to be ignored. aluminum electrolytic and tantalum capacitors have higher esr that must be included in load step calculations. the output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. the catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. a typical load step response is shown in figure 36 . the excess energy absorbed in the output capacitor will increase the voltage on the capacitor. the capacitor must be sized to maintain the desired output voltage during these transient periods. equation 31 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where l o is the value of the inductor, i oh is the output current under heavy load, i ol is the output under light load, v f is the peak output voltage, and vi is the initial voltage. for this example, the worst case load step will be from 3.75 a to 1.25 a. the output voltage increases during this load transition and the stated maximum in our specification is 4 % of the output voltage. this makes v f = 1.04 5 = 5.2. vi is the initial capacitor voltage which is the nominal output voltage of 5 v. using these numbers in equation 31 yields a minimum capacitance of 44.1 f. equation 32 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ? sw is the switching frequency, v oripple is the maximum allowable output voltage ripple, and i ripple is the inductor ripple current. equation 32 yields 19.9 f. equation 33 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. equation 33 indicates the esr should be less than 15.7 m . copyright ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links: tps54560 ( ) ripple out l peak i 1.591 a i i 5 a 5.797 a 2 2 = + = + = ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2 2 out out in max 2 2 out l rms o sw in max v v v 5 v 60 v - 5 v 1 1 i i 5 a 5 a 12 v l 12 60 v 7.2 h 400 khz ? ? - ? ? ? = + = + = ? ? ? m ? ? ? f ( ) ( ) out out in max ripple o sw in max v (v v ) 5 v x (60 v - 5 v) i 1.591 a v l 60 v x 7.2 h x 400 khz - = = = m f ( ) ( ) ( ) out in max out o min out ind sw in max v v v 60 v - 5 v 5 v l 7.6 h i k v 5 a x 0.3 60 v 400 khz - = = = m f
tps54560 slvsbn0 ? march 2013 www.ti.com the most stringent criteria for the output capacitor is 62.5 f required to maintain the output voltage within regulation tolerance during a load transient. capacitance de-ratings for aging, temperature and dc bias increases this minimum value. for this example, 3 x 47 f, 10 v ceramic capacitors with 5 m of esr will be used. the derated capacitance is 87.4 f, well above the minimum required capacitance of 62.5 f. capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability. some capacitor data sheets specify the root mean square (rms) value of the maximum ripple current. equation 34 can be used to calculate the rms ripple current that the output capacitor must support. for this example, equation 34 yields 459 ma. (30) (31) (32) (33) (34) catch diode the tps54560 requires an external catch diode between the sw pin and gnd. the selected diode must have a reverse voltage rating equal to or greater than v in(max) . the peak current rating of the diode must be greater than the maximum inductor current. schottky diodes are typically a good choice for the catch diode due to their low forward voltage. the lower the forward voltage of the diode, the higher the efficiency of the regulator. typically, diodes with higher voltage and current ratings have higher forward voltages. a diode with a minimum of 60 v reverse voltage is preferred to allow input voltage transients up to the rated voltage of the tps54560. for the example design, the b560c-13-f schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. the typical forward voltage of the b560c-13-f is 0.70 volts at 5 a. the diode must also be selected with an appropriate power rating. the diode conducts the output current during the off-time of the internal power switch. the off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. the output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. at higher switching frequencies, the ac losses of the diode need to be taken into account. the ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. equation 35 is used to calculate the total power dissipation, including conduction losses and ac losses of the diode. the b560c-13-f diode has a junction capacitance of 300 pf. using equation 35 , the total loss in the diode at the maximum input voltage is 3.43 watts. if the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop. 24 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 ( ) ( ) ( ) ( ) out out in max cout(rms) o sw in max v v v 5 v 60 v - 5 v i 459 ma 12 v l 12 60 v 7.2 h 400 khz f - = = = m oripple esr ripple v 25 mv r 15.7 m i 1.591 a < = = w out sw oripple ripple 1 1 1 1 c x 19.9 f 25 mv 8 8 x 400 khz v 1.591 a i > = = m ? ? ? ? ? ? ? ? f ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2 2 2 2 oh ol out o 2 2 2 2 f i i - i 3.75 a - 1.25 a c l x 7.2 h x 44.1 f 5.2 v 5 v v - v > = m = m - out out sw out 2 i 2 2.5 a c 62.5 f v 400 khz x 0.2 v d > = = m d f
tps54560 www.ti.com slvsbn0 ? march 2013 (35) input capacitor the tps54560 requires a high quality ceramic type x5r or x7r input decoupling capacitor with at least 3 f of effective capacitance. some applications will benefit from additional bulk capacitance. the effective capacitance includes any loss of capacitance due to dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum input current ripple of the tps54560. the input ripple current can be calculated using equation 36 . the value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. x5r and x7r ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the input capacitor must also be selected with consideration for the dc bias. the effective value of a capacitor decreases as the dc bias across a capacitor increases. for this example design, a ceramic capacitor with at least a 60 v voltage rating is required to support the maximum input voltage. common standard ceramic capacitor voltage ratings include 4 v, 6.3 v, 10 v, 16 v, 25 v, 50 v or 100 v. for this example, four 2.2 f, 100 v capacitors in parallel are used. table 2 shows several choices of high voltage capacitors. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 37 . using the design example values, i out = 5 a, c in = 8.8 f, ? sw = 400 khz, yields an input voltage ripple of 355 mv and a rms input ripple current of 2.26 a. (36) (37) table 2. capacitor types vendor value ( f) eia size voltage dialectric comments 1 to 2.2 100 v 1210 grm32 series 1 to 4.7 50 v murata 1 100 v 1206 grm31 series 1 to 2.2 50 v 1 to 1.8 50 v 2220 1 to 1.2 100 v vishay vj x7r series 1 to 3.9 50 v 2225 1 to 1.8 100 v x7r 1 to 2.2 100 v 1812 c series c4532 1.5 to 6.8 50 v tdk 1 to 2.2 100 v 1210 c series c3225 1 to 3.3 50 v 1 to 4.7 50 v 1210 1 100 v avx x7r dielectric series 1 to 4.7 50 v 1812 1 to 2.2 100 v copyright ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links: tps54560 ( ) ( ) ( ) ( ) ( ) ( ) out in min out out ci rms in min in min v v 7 v - 5 v v 5 v i i x x 5 a 2.26 a v v 7 v 7 v - = = = ( ) ( ) ( ) ( ) ( ) 2 out out in max j sw in d in max 2 v v i v d c v v d p v 2 60 v - 5 v 5 a x 0.7 v 300 pf x 400 khz x (60 v 0.7 v) 3.43 w 60 v 2 f f f - + = + = + + = out in in sw i 0.25 5 a 0.25 v 355 mv c 8.8 f 400 khz d = = = m f
tps54560 slvsbn0 ? march 2013 www.ti.com bootstrap capacitor selection a 0.1- f ceramic capacitor must be connected between the boot and sw pins for proper operation. a ceramic capacitor with x5r or better grade dielectric is recommended. the capacitor should have a 10 v or higher voltage rating. undervoltage lockout set point the undervoltage lockout (uvlo) can be adjusted using an external voltage divider on the en pin of the tps54560. the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above 6.5 v (uvlo start). after the regulator starts switching, it should continue to do so until the input voltage falls below 5 v (uvlo stop). programmable uvlo threshold voltages are set using the resistor divider of r uvlo1 and r uvlo2 between vin and ground connected to the en pin. equation 2 and equation 3 calculate the resistance values necessary. for the example application, a 442 k between v in and en (r uvlo1 ) and a 90.9 k between en and ground (r uvlo2 ) are required to produce the 6.5 v and 5 v start and stop voltages. (38) (39) output voltage and feedback resistors selection the voltage divider of r5 and r6 sets the output voltage. for the example design, 10.2 k was selected for r6. using equation 1 , r5 is calculated as 53.5 k . the nearest standard 1% resistor is 53.6 k . due to the input current of the fb pin, the current flowing through the feedback network should be greater than 1 a to maintain the output voltage accuracy. this requirement is satisfied if the value of r6 is less than 800 k . choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but may also introduce noise immunity problems. (40) compensation there are several methods to design compensation for dc-dc regulators. the method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. since the slope compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the calculations. this method assumes the crossover frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. to get started, the modulator pole, ? p(mod) , and the esr zero, ? z1 must be calculated using equation 41 and equation 42 . for c out , use a derated value of 87.4 f. use equations equation 43 and equation 44 to estimate a starting point for the crossover frequency, ? co. for the example design, ? p(mod) is 1821 hz and ? z(mod) is 1100 khz. equation 42 is the geometric mean of the modulator pole and the esr zero and equation 44 is the mean of modulator pole and half of the switching frequency. equation 43 yields 44.6 khz and equation 44 gives 19.1 khz. use the geometric mean value of equation 43 and equation 44 for an initial crossover frequency. for this example, after lab measurement, the crossover frequency target was increased to 30 khz for an improved transient response. next, the compensation components are calculated. a resistor in series with a capacitor is used to create a compensating zero. a capacitor in parallel to these two components forms the compensating pole. (41) (42) 26 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 ( ) z mod esr out 1 1 1100 khz 2 r c 2 1.67 m 87.4 f = = = p p w m f ( ) ( ) out max p mod out out i 5 a 1821 hz 2 v c 2 5 v 87.4 f = = = p p m f ? ? = = w = w ? ? out hs ls v - 0.8 v 5 v - 0.8 v r r x 10.2 k x 53.5 k 0.8 v 0.8 v ena uvlo2 start ena 1 uvlo1 v 1.2 v r 90.9 k v - v 6.5 v - 1.2 v 1.2 a i 442 k r = = = w + m + w
tps54560 www.ti.com slvsbn0 ? march 2013 (43) (44) to determine the compensation resistor, r4, use equation 45 . assume the power stage transconductance, gmps, is 17 a/v. the output voltage, v o , reference voltage, v ref , and amplifier transconductance, gmea, are 5 v, 0.8 v and 350 a/v, respectively. r4 is calculated to be 16.8 k and a standard value of 16.9 k is selected. use equation 46 to set the compensation zero to the modulator pole frequency. equation 46 yields 5172 pf for compensating capacitor c5. 4700 pf is used for this design. (45) (46) a compensation pole can be implemented if desired by adding capacitor c8 in parallel with the series combination of r4 and c5. use the larger value calculated from equation 47 and equation 48 for c8 to set the compensation pole. the selected value of c8 is 47 pf for this design example. (47) (48) discontinuous conduction mode and eco-mode boundary with an input voltage of 12 v, the power supply enters discontinuous conduction mode when the output current is less than 408 ma. the power supply enters eco-mode when the output current is lower than 25.3 ma. the input current draw is 257 a with no load. copyright ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links: tps54560 co out out ref 2 c v 2 29.2 khz 87.4 5v r4 x x 16.8 k gmps v x gmea 17 a / v 0.8 v x 350 a / v ? ? p ? ? ? ? p m ? ? = = = w ? ? ? ? m ? ? ? ? f f sw co2 p(mod) x 400 khz 1821 hz x 19.1 khz 2 2 = = = f f f co1 p(mod) x z(mod) 1821 hz x 1100 khz 44.6 khz = = = f f f 1 1 c8 47.1 pf r4 x sw x 16.9 k x 400 khz x = = = p w p f out esr c x r 87.4 f x 1.67 m c8 8.64 pf r4 16.9 k m w = = = w p(mod) 1 1 c5 5172 pf 2 r4 x 2 16.9 k x 1821 hz = = = p p w f
tps54560 slvsbn0 ? march 2013 www.ti.com application curves measurements are taken with standard evm using a 12v input, 5v output, and 5a load unless otherwise noted. figure 36. load transient figure 37. line transient (8 v to 40 v) figure 38. start-up with vin figure 39. start-up with en 28 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 4 v/div 5 v/div vin vout time = 2 ms/div en 1 v/div 4 v/div 5 v/div vin vout time = 2 ms/div en 2 v/div time = 100 p s/div 200 mv/div 1 a/div iout vout 5v offset 10 mv/div 10 v/div vin vout 5v offset time = 4 ms/div
tps54560 www.ti.com slvsbn0 ? march 2013 measurements are taken with standard evm using a 12v input, 5v output, and 5a load unless otherwise noted. figure 40. output ripple ccm figure 41. output ripple dcm figure 42. output ripple psm figure 43. input ripple ccm figure 44. input ripple dcm figure 45. low dropout operation copyright ? 2013, texas instruments incorporated submit documentation feedback 29 product folder links: tps54560 200 mv/div 10 v/div sw vin ac coupled time = 4 p s/div il 1 m\a/div 10 mv/div 10 v/div sw vout ac coupled time = 4 p s/div il 1 a/div 10 mv/div 10 v/div sw vout ac coupled time = 4 p s/div il 500 ma/div i out = 100 ma 20 mv/div 2 v/div sw vout time = 40 p s/div il 200 ma/div no load en floating v in = 5.5 v 10 mv/div 10 v/div sw vin ac coupled time = 4 p s/div il 500 ma/div i out = 100 ma 10 mv/div 10 v/div sw vout ac coupled time = 1 ms/div il 200 ma/div no load
tps54560 slvsbn0 ? march 2013 www.ti.com measurements are taken with standard evm using a 12v input, 5v output, and 5a load unless otherwise noted. figure 46. low dropout operation figure 47. low dropout operation figure 48. efficiency vs load current figure 49. light load efficiency figure 50. efficiency vs load current figure 51. light load efficiency 30 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 efficiency (%) i o - output current (a) 6v 12v 24v 36v 48v 60v c024 v in = 12 v v in = 24 v v in = 36 v v in = 48 v v in = 60 v v out = 3.3 v, f sw = 400 khz v in = 6 v 0 10 20 30 40 50 60 70 80 90 100 0.00 0.01 0.10 1.00 efficiency (%) i o - output current (a) 6v 12v 24v 36v 48v 60v c024 v in = 12 v v in = 24 v v in = 36 v v in = 48 v v in = 60 v v out = 3.3 v, f sw = 400 khz v in = 6 v 0.001 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 efficiency (%) i o - output current (a) series1 12v 24v 36v 48v 60v c024 v in = 12 v v in = 24 v v in = 36 v v in = 48 v v in = 60 v v out = 5 v, f sw = 400 khz v in = 7 v 0 10 20 30 40 50 60 70 80 90 100 0.00 0.01 0.10 1.00 efficiency (%) i o - output current (a) 7v 12v 24v 36v 48v 60v c024 v in = 12 v v in = 24 v v in = 36 v v in = 48 v v in = 60 v v out = 5 v, f sw = 400 khz v in = 7 v 0.001 time = 40 s/div m 2 v/div v in i = 100 ma en floating out v out time = 40 s/div m 2 v/div v in i = 1 a en floating out v out
tps54560 www.ti.com slvsbn0 ? march 2013 measurements are taken with standard evm using a 12v input, 5v output, and 5a load unless otherwise noted. figure 52. efficiency vs output current figure 53. overall loop frequency response figure 54. regulation vs load current figure 55. regulation vs input voltage copyright ? 2013, texas instruments incorporated submit documentation feedback 31 product folder links: tps54560 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output voltage normalized (%) i o - output current (a) c024 v in = 12 v, v out = 5 v, f sw = 400 khz 60 65 70 75 80 85 90 95 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 efficiency (%) i o - output current (a) 18in series1 series3 series6 series8 c024 v in = 18 v v in = 24 v v in = 36 v v in = 48 v v in = 60 v v out = 12 v, f sw = 800 khz 180 150 120 90 60 30 0 30 60 90 120 150 180 60 50 40 30 20 10 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m phase ( ? ) gain (db) frequency (hz) gain phase c001 v in = 12 v v out = 5 v i out = 5 a 0.3 0.2 0.1 0.0 0.1 0.2 0.3 5 10 15 20 25 30 35 40 45 50 55 60 output voltage normalized (%) v i - input voltage (v) c024 v out = 5 v, i out = 5 a, f sw = 400 khz
tps54560 slvsbn0 ? march 2013 www.ti.com power dissipation estimate the following formulas show how to estimate the tps54560 power dissipation under continuous conduction mode (ccm) operation. these equations should not be used if the device is operating in discontinuous conduction mode (dcm). the power dissipation of the ic includes conduction loss (p cond ), switching loss (p sw ), gate drive loss (p gd ) and supply current (p q ). example calculations are shown with the 12 v typical input voltage of the design example. (49) spacer (50) spacer (51) spacer (52) where: i out is the output current (a). r ds(on) is the on-resistance of the high-side mosfet ( ). v out is the output voltage (v). v in is the input voltage (v). fsw is the switching frequency (hz). trise is the sw pin voltage rise time and can be estimated by trise = v in x 0.16 ns/v + 3 ns q g is the total gate charge of the internal mosfet i q is the operating nonswitching supply current therefore, (53) for given t a , (54) for given t jmax = 150 c (55) where: ptot is the total device power dissipation (w). t a is the ambient temperature ( c). t j is the junction temperature ( c). r th is the thermal resistance of the package ( c/w). t jmax is maximum junction temperature ( c). t amax is maximum ambient temperature ( c). there will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode and pcb trace resistance impacting the overall efficiency of the regulator. 32 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 ( ) ( ) = - th tot a max j max t t r p = + j a th tot t t r p tot cond sw gd q p p p p p 0.958 w 0.118 w 0.014 w 0.0018 w 1.092 w = + + + = + + + = = = m = q in q p v i 12 v 146 a 0.0018 w gd in g sw p v q 12 v 3nc 400 khz 0.014 w = = = f sw in sw out rise p v i t 12 v 400 khz 5 a 4.9 ns 0.118 w = = = f ( ) ( ) 2 2 out cond out ds on in v 5 v p i r 5 a 92 m 0.958 w v 12 v ? ? = = w = ? ?
tps54560 www.ti.com slvsbn0 ? march 2013 safe operating area the safe operating area (soa) of the device is shown in figure 56 , through figure 59 for 3.3 v, 5 v and 12 v outputs and varying amounts of forced air flow. the temperature derating curves represent the conditions at which the internal components are at or below the manufacturer ? s maximum operating temperatures. derating limits apply to devices soldered directly to a double-sided pcb with 2 oz. copper, similar to the evm. careful attention must be paid to the other components chosen for the design, especially the catch diode. figure 56. 3.3v outputs figure 57. 5v outputs figure 58. 12v outputs figure 59. air flow conditions v in = 36 v, v o = 12 v copyright ? 2013, texas instruments incorporated submit documentation feedback 33 product folder links: tps54560 20 30 40 50 60 70 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a ( ? c) i out (amps) 18 v 24 v 36 v 48 v 60 v c048 f sw = 800 khz 20 30 40 50 60 70 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a ( ? c) i out (amps) 400 lfm 200 lfm 100 lfm nat conv c048 20 30 40 50 60 70 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a ( ? c) i out (amps) 6 v 12 v 24 v 36 v 48 v 60 v c047 20 30 40 50 60 70 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a ( ? c) i out (amps) 8 v 12 v 24 v 36 v 48 v 60 v c048
tps54560 slvsbn0 ? march 2013 www.ti.com layout layout is a critical portion of good power supply design. there are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. to reduce parasitic effects, the vin pin should be bypassed to ground with a low esr ceramic bypass capacitor with x5r or x7r dielectric. care should be taken to minimize the loop area formed by the bypass capacitor connections, the vin pin, and the anode of the catch diode. see figure 60 for a pcb layout example. the gnd pin should be tied directly to the power pad under the ic and the power pad. the power pad should be connected to internal pcb ground planes using multiple vias directly under the ic. the sw pin should be routed to the cathode of the catch diode and to the output inductor. since the sw connection is the switching node, the catch diode and output inductor should be located close to the sw pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. for operation at full rated load, the top side ground area must provide adequate heat dissipating area. the rt/clk pin is sensitive to noise so the rt resistor should be located as close as possible to the ic and routed with minimal lengths of trace. the additional external components can be placed approximately as shown. it may be possible to obtain acceptable performance with alternate pcb layouts, however this layout has been shown to produce good results and is meant as a guideline. figure 60. pcb layout example estimated circuit area boxing in the components in the design of figure 35 the estimated printed circuit board area is 1.025 in 2 (661 mm 2 ). this area does not include test points or connectors. 34 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links: tps54560 bootvin en rt/clk sw gnd comp fb inputbypass capacitor uvloadjust resistors frequencyset resistor compensationnetwork resistordivider outputinductor output capacitor vout vin topside ground area catchdiode route boot capacitor trace on another layer to provide wide path for topside ground thermal via signal via
tps54560 www.ti.com slvsbn0 ? march 2013 figure 61. tps54560 inverting power supply from slva317 application note figure 62. tps54560 split rail power supply based on the slva369 application note copyright ? 2013, texas instruments incorporated submit documentation feedback 35 product folder links: tps54560 sw vin gnd boot fb comp tps54560 en rt/clk cpole czero rcomp rt coneg lo cboot cin r1 r2 cd vin voneg + + gnd vopos copos + sw vin gnd boot fb comp tps54560 en rt/clk cpole czero rcomp rt co lo cboot cin r1 r2 cd vin vout + + gnd
package option addendum www.ti.com 21-jul-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) device marking (4/5) samples TPS54560DDA active so powerpad dda 8 75 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 150 54560 TPS54560DDAr active so powerpad dda 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 150 54560 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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